Apparatus and methods for electrochemical processing of microfeature wafers

ABSTRACT

Methods for electrochemically processing microfeature wafers using at least one counter electrode in a vessel, a supplementary electrode and a supplementary virtual electrode. The supplementary electrode is configured to operate independently from the counter electrode in the vessel, and it can be a thief electrode and/or a de-plating electrode depending. The supplementary electrode can further be used as another counter electrode during a portion of a plating cycle or polishing cycle. The supplementary virtual electrode is located in the processing zone, and it is configured to counteract an electric field offset relative to the wafer associated with an offset between the wafer and the counter electrode.

TECHNICAL FIELD

This application is a Continuation of U.S. patent application Ser. No.12/917,997, filed Nov. 2, 2010, and now pending, which is a Division ofU.S. patent application Ser. No. 11/699,768, filed Jan. 29, 2007, nowU.S. Pat. No. 7,842,173, and incorporated herein by reference. Thisapplication relates to apparatus and methods for electroplating and/orelectropolishing microfeature wafers that have a plurality ofmicrofeatures integrated in and/or on the wafers. Particular apparatusand methods of the present invention ameliorate non-uniformities causedby misalignment between the wafer and the electrodes, provide goodcontrol of the current density across the wafer, mitigate particlecontamination, and reduce the downtime for cleaning thief electrodes inelectrochemical processes used in the manufacturing of semiconductordevices, imagers, storage media and other products.

BACKGROUND

Microelectronic devices, such as semiconductor devices, imagers,displays, storage media, and micromechanical components, are generallyfabricated on and/or in microfeature wafers using a number of processesthat deposit and/or remove materials from the wafers. Electroplating isone such process that deposits conductive, magnetic or electrophoreticlayers on the wafers. Electroplating processes, for example, are widelyused to form small copper interconnects or other very small sub-micronfeatures in trenches and/or holes (e.g., less than 90 nm damascenecopper lines). Electropolishing is another process that removes materialfrom a wafer. In both of these processes, an electrical current ispassed between the wafer and one or more counter electrodes in a mannerthat deposits or removes material from a surface of the wafer.

One challenge of plating materials into narrow, deep recesses is that itis very difficult to completely fill the very small features and createa desired surface profile on the plated layer (e.g., uniformly planar,domed, etc.). For example, as the performance of microelectronicproducts increase, the aspect ratios and densities of the recessessubstantially increases. To adequately fill such small, high densityrecesses with high aspect ratios, existing plating practices often platea metal onto a very thin seed layer or directly onto a barrier layer.Thin seed layers and barrier layers, however, typically have relativelyhigh resistances that cause a significant drop in current density fromthe edge of the wafer to the center during the initial stages of aplating cycle. The plating rate at the edge of the wafer is accordinglysignificantly higher than the center during the initial portion of theplating process, which causes the plated material at the edge of thewafer to be substantially thicker than the middle. This edge effect isfurther exacerbated by the higher densities and higher aspect ratios ofthe recesses. Therefore, reducing or eliminating the edge effect is asignificant challenge that needs to be addressed to develop faster,higher performance semiconductor devices and other microfeature devices.

Several existing plating tools have reactors with a thief electrodeattached to the wafer holder to mitigate the edge effect caused by highresistance of the wafer or by the geometry of the chamber. The thiefelectrode is biased at the same polarity as the wafer such that itmodifies the electric field in the perimeter region of the wafer. Thethief electrode accordingly reduces the plating rate at the perimeter ofthe wafer to compensate for the edge effect. Although such systems maymitigate the edge effect, they also have several disadvantages. First,particles that build up on the thief electrode may eventually becomedislodged, and the close proximity of the thief electrode increases thelikelihood that the dislodged particles will plate or otherwise adhereto the wafer. Moreover, it is difficult to minimize the formation ofparticles on a thief electrode attached to a wafer holder because thethief electrode is removed from the bath to unload finished wafers andload new wafers, and then the thief is reintroduced into the platingbath with each new wafer. Such wetting and drying of the film on thethief can make it difficult to control the quality of film on the waferand minimize particles. It is also difficult to clean and maintain thiefelectrodes when they are attached to the wafer holder. This isproblematic because thief electrodes must be cleaned relatively often,and it requires a significant amount of time and effort to detach thethief electrode from the wafer holder. Therefore, existing systems withthief electrodes carried by the wafer holder have several drawbacks.

Other types of systems have a plurality of anodes, a thief electrodeseparate from the wafer holder, and a virtual thief electrode defined byan aperture having a fixed size under the wafer. Such systems withdetached thief electrodes generally position the thief electrode in thebottom portion of the reactor vessel. The present inventors havediscovered that systems with virtual thief openings improve theperformance of the reactors, but they also present additionalchallenges. One improvement is that dislodged particles from the thiefelectrode are not as likely to plate onto the wafer because thiefelectrode is not as close to the wafer. However, one disadvantage of notattaching the thief electrode to the wafer holder is that the systemsare sensitive to misalignment between the wafer holder and the thiefelectrode or the anode(s). This is because the thief electrodes arefixed relative to the vessels of the chamber, but the wafer holder andvessel may not be properly aligned with each other, which causesmisalignment between the wafer holder and the thief electrode or theanode(s). Such misalignment can lead to a side-to-side non-uniformity ofthe film plated onto the wafer, and is particularly problematic insystems in which the wafer is held stationary during processing (e.g.,plating a magnetic alloy). This is not as problematic in systems inwhich the wafer is rotated during processing because any side-to-sidenon-uniformity can be average out, which greatly reduces the sensitivityof the system misalignment.

Another disadvantage of systems with detached thief electrodes is thatthey are highly dependent upon the geometry of the chamber to reduce theedge effect even when a thief electrode is used. For example, manyexisting systems use a shield below the wafer to block a perimeterportion of the wafer from the anodes. Such shields may limit the abilityof the thief electrode to adequately control the current density at theperimeter of the wafer. The physical geometry of the chamber mayaccordingly limit the ability to control the edge effect. Although thisis useful in specific plating applications, a plating tool is often usedto process different types of wafers with different types of devices.Conventional systems accordingly require different shields for platingonto different wafers in many circumstances. This is problematic becauseit requires the chamber to be drained, partially disassembled,reassembled with a new shield, and then refilled and recalibrated forprocessing. This is an expensive and time consuming process to adapt thechamber to plate different types of wafers.

Still another disadvantage of several existing systems with detachedthief electrodes is that the thief electrode is located in a lowerportion of the chamber. The reaction chambers accordingly need to bedrained and partially disassembled to access the thief electrode forcleaning. This is also an expensive and time-consuming process.Therefore, even though thief electrodes have been used in manyelectroplating apparatus for fabricating semiconductor devices, there isa significant need to improve electroplating chambers to plate materialsinto high density features with high aspect ratios.

In light of the foregoing, it would be desirable to provide an apparatusand method that ameliorates non-uniformities caused by an offset betweenthe wafer holder and the vessel, reduces particle contaminationassociated with thief electrodes, and makes it easier to clean andmaintain thief electrodes. It would also be desirable to provideelectrochemical processing apparatus and methods that can compensate forseed layer or barrier layer resistance, or changes in the bathconductivity, to provide a desired current density across the wafer.There is also a need for a reactor that provides the ability to furthercontrol the surface profile of the plated layer across the diameter ofthe wafer.

SUMMARY

The present invention provides apparatus and methods forelectrochemically processing microfeature workpieces that are capable ofcompensating or otherwise ameliorating many non-uniformities caused byan offset between the wafer holder and the electrodes. The apparatus andmethods are further capable of providing better control of the currentdensity across the wafer to compensate for seed layer resistance,barrier layer resistance, and/or bath conductivity. To overcome theproblems and challenges of existing thief electrode designs, the presentinventors developed an apparatus in which the combination of asupplementary electrode and an associated supplementary virtualelectrode mitigate particle contamination, ameliorate non-uniformitiescaused by wafer-anode misalignment, and provide better control of theedge effect associated with high density features. The supplementaryelectrode and the supplementary virtual electrode are configured toself-compensate for misalignment between the wafer holder and theanodes. This is accomplished by, at least in part, forming an aperturethat defines the virtual supplementary electrode using a portion of thevessel and a portion of the wafer holder. The shape of the aperture isrelated to the extent and orientation of the offset between the waferand the anodes so that the aperture is narrower on one side where thewafer holder is closer to the supplementary electrode and wider on theother side where the wafer is further from the supplementary electrode.Another feature that compensates for misalignment between the waferholder and the electrodes is that the supplementary electrode is closeto the supplementary virtual electrode. As a result, even smallwafer-anode misalignments (e.g., 0.5-1.0 mm) can produce relativelysignificant changes in the effect of the supplementary electrode onopposing sides of the wafer. Mechanical alignment to this accuracy isdifficult across multiple chambers in a production environment. Thesefeatures together or separately counteract non-uniformities associatedwith misalignment between the wafer holder and the vessel.

The apparatus and methods also provide easy cleaning of the thiefelectrode. This is accomplished by locating the supplementary electrodewhere it is separate from the wafer holder and above the vessel. Thesupplementary electrode can accordingly be removed from the chamberwithout having to disassemble significant portions of the vessel.Moreover, the supplementary electrode is positioned in the exit flow ofthe processing fluid outside of the processing zone such that particlesfrom the supplementary electrode are entrained in the flow of theprocessing fluid downstream from the wafer. The particles can then befiltered before the processing fluid is recirculated back into thechamber. As a result, the upper location of the supplementary electrodeand its position in the exit flow of the processing fluid provide easycleaning and mitigate particle contamination.

The apparatus and methods further provide good control of the currentdensity to enhance the uniformity or otherwise provide the desiredsurface profile on the plated layer. The apparatus accomplishes this, inpart, by configuring the supplementary electrode, the supplementaryvirtual electrode, and the vessel so that the supplementary electrode isnot limited by the chamber geometry and has a strong influence on thecurrent density at the perimeter of the wafer. More specifically, thesupplementary virtual electrode is located in the processing zone atleast proximate to the edge of the wafer and the supplementary electrodeis positioned close to the supplementary virtual electrode. Therefore,the current density and plating profiles can be controlled bydynamically changing the current to the supplementary electrode withouthaving to change the physical geometry of the chamber. This isparticularly useful when plating different types of wafers in the sameapparatus because the different perimeter characteristics of thedifferent wafers can be addressed using the current applied to thesupplementary electrode instead of having to change the shields or othercomponents associated with the chamber geometry. The current density maybe further controlled by using the configuration of the supplementaryelectrode and the supplementary virtual electrode in combination with aplurality of anodes and/or virtual anodes in the vessel.

Apparatus in accordance with the invention can have a vessel including aprocessing zone in which a microfeature wafer is positioned forelectrochemical processing. The apparatus further includes at least onecounter electrode in the vessel that can operate as an anode or acathode depending upon the particular plating or electropolishingapplication. The apparatus further includes a supplementary electrodeand a supplementary virtual electrode. The supplementary electrode isconfigured to operate independently from the counter electrode in thevessel. The supplementary electrode can be a thief electrode biased atthe same polarity as the wafer. The supplementary electrode canalternatively be a de-plating electrode for de-plating ring contactsbetween processing cycles, or the supplementary electrode can further beused as another counter electrode biased opposite the wafer during aportion of a plating cycle or polishing cycle. The supplementary virtualelectrode is located in the processing zone, and it is configured tocounteract an electric field offset relative to the wafer associatedwith an offset between the wafer and the counter electrode in the vesselwhen the wafer is in the processing zone.

The supplementary virtual electrode, more specifically, can have anaperture for shaping an electric field component from the supplementaryelectrode such that the aperture is formed, at least in part, by aportion of the vessel and a portion of a wafer holder in which the waferis positioned. In operation, misalignment between the wafer holder andthe vessel causes the aperture to have a first width at one side of thewafer holder and a second width different than the first width at anopposing side of the wafer holder. For example, the aperture can have anarrower width at the side of the vessel where the wafer holder iscloser to the supplementary electrode compared to an opposing side wherethe wafer holder is further from the supplementary electrode. Thenarrower portion of the aperture reduces the effect of the supplementaryelectrode at that side, while the wider portion of the apertureincreases the effect of the supplementary electrode at the opposingside. The different effect of the supplementary electrode on thedifferent sides of the wafer holder self-compensates for thecorresponding offset between the wafer holder and the counter electrode.As a result, the apparatus mitigates or ameliorates non-uniformitiesassociated with an offset between the wafer holder and the vessel whenthe wafer holder holds a wafer in the processing zone.

In summary, the apparatus and methods for electrochemically processingmicrofeature wafers provide several advantages for electroplating and/orelectropolishing processes. First, the configuration of thesupplementary electrode and the supplementary virtual electrodeself-compensate for offsets between the wafer holder and the counterelectrodes. This accordingly enables a thief electrode and/or ade-plating electrode to be located apart from the wafer holder. Second,because the supplementary electrode is not attached the wafer holder, itcan be located where it can be easily removed for cleaning and/or wheredislodged particles can be swept away from the processing zone. Third,positioning the supplementary virtual electrode in the processing zoneat a location relative to the vessel where dielectric shields cannotlimit the electric field of the supplementary electrode enables thesupplementary electrode to have a strong influence on the currentdensity in the periphery of the wafer. This feature allows thesupplementary electrode to effectively control the current density inthe periphery of the wafer. As such, it is easier to plate differenttypes of the wafers in the apparatus compared to existing systems inwhich control of the current density in the periphery of the wafer islimited by the geometry of the vessel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a side view of an apparatus in accordance with an embodimentof the invention in which a portion is shown in cross-section andanother portion is shown schematically.

FIG. 2 is an isometric view illustrating a portion of the apparatus ofFIG. 1 in greater detail.

FIG. 3 is a cross-sectional view illustrating one aspect of operating anapparatus in accordance with an embodiment of the invention.

FIG. 4 is a cross-sectional view illustrating another aspect ofoperating the apparatus of FIG. 3.

FIG. 5 is a side view of an apparatus in accordance with the inventionin which a portion of the apparatus is shown in cross-section andanother portion is shown schematically.

FIG. 6 is a side view of an apparatus in accordance with anotherembodiment of the invention in which a portion of the apparatus is shownin cross-section and another portion is shown schematically.

FIG. 7 is a cross-sectional isometric view of an apparatus in accordancewith a specific embodiment of the invention.

FIG. 8 is a cross-sectional view of the specific embodiment shown inFIG. 7.

FIG. 9 is a cross-sectional view of another embodiment of the invention.

FIG. 10 is a cross-sectional view of another embodiment of theinvention.

DETAILED DESCRIPTION

FIGS. 1-8 illustrate several embodiments of apparatus and methods forelectrochemically processing microfeature wafers. As used herein, theterms “microfeature wafer” or “wafer” refer to substrates on and/or inwhich microfeatures are formed. Typical microfeatures includemicroelectronic circuits or components, thin-film recording heads, datastorage elements, microfluidic devices, and other products.Micromachines or micromechanical devices are included within thisdefinition because they are manufactured using much of the sametechnology that is used in the fabrication of integrated circuits and/orstorage elements. The wafers can be semiconductor pieces (e.g., siliconwafers, gallium arsenide wafers, etc.), non-conductive pieces (e.g.,ceramic substrates, glass, etc.), or conductive pieces (e.g., dopedwafers, conductive substrates, etc.). Also, the term “electrochemicalprocessing” includes electroplating, electro-etching, electropolishing,and/or anodization. Several specific details of the invention are setforth in the following description and in FIGS. 1-8 to provide athorough understanding of certain embodiments of the invention. Oneskilled in the art, however, will understand that the present inventionmay have additional embodiments, or that other embodiments of theinvention may be practiced without several of the specific featuresexplained in the following description.

FIG. 1 is a side view of an apparatus 100 for electrochemicallyprocessing a wafer W. The apparatus 100 includes a vessel 110 having aprocessing zone Z in which a surface S of the wafer W can be positionedfor electrochemical processing. The vessel 110 is configured to containa flow of processing fluid, and at least one counter electrode (notshown in FIG. 1) is positioned in the vessel 110. The wafer W can beelectrically connected to a power supply such that the wafer W is aworking electrode that acts as either an anode or cathode, and thecounter electrode in the vessel acts as the other of the cathode oranode. The apparatus 100 further includes a supplementary electrode 120that is configured to operate independently from the counter electrodein the vessel, and a supplementary virtual electrode 130 in, or at leastproximate to, the processing zone Z. The supplementary electrode 120 canbe a thief electrode that acts through the supplementary virtualelectrode 130 to control or otherwise influence the electric field at aperimeter portion of the wafer W. The supplementary electrode 120 andsupplementary virtual electrode 130 are configured to compensate formisalignment between the wafer W and the counter electrode in the vessel110 as explained in more detail below.

FIG. 2 is an isometric view of a portion of the apparatus 100 that showsseveral features in greater detail. Referring to FIGS. 1 and 2 together,the apparatus 100 can further include a wafer holder 140 having asupport 142 configured to hold the wafer W in the processing zone Z. Thesupport 142, more specifically, is configured to hold the surface S ofthe wafer W face down in a horizontal orientation in contact with aprocessing fluid flowing upwardly through the processing zone Z. Thewafer holder 140 also has at least one electrical contact 144 configuredto provide an electrical current to the wafer W. The wafer holder 140,for example, can have a contact configured to contact the backside ofthe wafer W as shown and described in U.S. Patent Publication No.US2005-0006241A1, which is incorporated herein by reference. The waferholder 140 can alternatively include a plurality of electrical contacts144 configured to engage a perimeter portion of the surface S of thewafer W either in lieu of or in addition to a backside contact. Suitablewafer holders 140 with a plurality of electrical contacts 144 are shownand described in U.S. Pat. Nos. 6,080,291; 6,527,925; 6,773,560; andU.S. Patent Publication No. 2006-0289302A1, all of which areincorporated herein by reference. The wafer holder 140 may also includea seal at the lower lip of the support configured to seal against aperimeter portion of the surface S of the workpiece W.

As also shown in FIGS. 1 and 2, the vessel 110 can further include amember 112 with an inner edge 114, a rim 116 above the inner edge 114,and a perimeter 118. In the example of the apparatus 100 shown in FIG.2, the inner edge 114 of the member 112 is positioned in a planecorresponding to a portion of the support 142 such that thesupplementary virtual electrode 130 has an aperture defined by the spacebetween the inner edge 114 and the support 142. The aperture of thevirtual supplementary electrode 130 can be in a plane that is at leastgenerally parallel to a processing plane of the wafer W and located at alower portion of the wafer holder 140. The shape of the aperture of thesupplementary virtual electrode 130 is accordingly a function of thespace between the support 142 and the inner edge 114 such that theaperture will be narrower on one side of the wafer holder 140 and wideron an opposing side when the wafer holder 140 and the vessel 110 aremisaligned with each other relative to an axis A-A (FIG. 1). Theaperture of the supplementary virtual electrode 130, for example, canhave a first width at one side of the wafer holder 140 and a secondwidth different than the first width at another side of the wafer holder140 corresponding to the degree of misalignment between the wafer holder140 and the vessel 110. Therefore, as explained in more detail below,the supplementary virtual electrode 130 self-compensates for anymisalignment between the wafer holder 140 and the vessel 110 tocounteract a corresponding offset between the wafer W and a counterelectrode in the vessel 110.

The apparatus 100 can further include a mount 150 above the member 112.Referring to FIG. 2, the mount 150 and the member 112 form a compartment151 having a first flow outlet 152 through which a portion of theprocessing fluid can exit the processing zone and flow over theperimeter 118 of the vessel 110. The compartment 151 is also configuredto contain the supplementary electrode 120 at a location above theprocessing zone Z. In the example illustrated in FIG. 2, thesupplementary electrode 120 is located above the member 112 at a radialposition between the inner edge 114 and the perimeter 118. Thesupplementary electrode 120 can be attached to the mount 150 by a numberof posts or tabs 122 to suspend the supplementary electrode 120 in thecompartment 151 between the mount 150 and the member 112. In analternative embodiment, the supplementary electrode can be embeddedwithin a recess 123 (shown in broken lines) in the underside of themount 150. It is generally preferable to have the supplementaryelectrode 120 suspended in the compartment 151 to avoid chemicals fromcollecting in such a recess, and also to provide additional surface areafor the supplementary electrode 120 to contact the processing fluid. Thesupplementary electrode 120 can be coupled to a power supply via aconnector 126.

The mount 150 further includes a brim 154 and a plurality of optionalchannels 156 (shown in broken lines) through which the processing fluidcan flow between the mount 150 and the wafer holder 140. The channels156 accordingly provide a second flow outlet for the processing fluid.The flow of processing fluid through the channels 156 wets the brim 154and the upwardly facing inclined surface of the mount 150 to avoidcrystal formation on the top of the mount 150 that can occur when theprocessing fluid dries. As explained in more detail below, this featureenables the wafer holder 140 to bottom out against the brim 154 withoutcontacting crystal formations on top of the mount 150 to avoid skewingthe wafer holder at an improper angle.

FIGS. 3 and 4 are cross-sectional views illustrating the operation andadvantages of the apparatus 100. FIG. 3, more specifically, illustratesthe apparatus 100 during a state without a wafer in position forprocessing. The processing fluid F flows upwardly U through an openingdefined by the member 112. The upper level of the processing fluid F isdefined by the brim 154 of the mount 150; the brim 154 accordingly actsas a weir, and the fluid height of the processing fluid F is generallyslightly above the height of the brim 154. The processing fluid F flowsover the top of the brim 154 and the upwardly facing inclined surface ofthe mount 150 between processing cycles to avoid crystal formations onthe top of the mount 150. This feature mitigates misalignment of thewafer holder during processing that can be caused by crystal formationson top of the brim 154. A portion of the processing fluid F also flowsthrough the compartment 151 and through the outlet 152. This portion ofprocessing fluid F flows outwardly past the perimeter 118 of the vessel110 to carry away particles that are dislodged from the supplementaryelectrode 120. The processing fluid F is then filtered to removeparticles, bubbles and other contaminants before it is recycled throughthe vessel 110.

FIG. 4 illustrates the apparatus 100 during a processing cycle after thewafer holder 140 has positioned the wafer W in processing plane in theprocessing zone Z. The supplementary electrode 120 is activated duringthe processing cycle to provide an electric field component that actsthrough the supplementary virtual electrode 130 for controlling thecurrent density in the perimeter region of the wafer W. In the exampleshown in FIG. 4, the central axis of the wafer holder 140 is misalignedrelative to the vessel 110 such that one side of the wafer holder 140 iscloser to the member 112 than the opposing side. When this occurs, thewidth of the supplementary virtual electrode 130 is narrower on the sideat which the wafer holder 140 is closer to the supplementary electrode120 (side A), and wider on the side where the wafer holder 140 isfurther from the supplementary electrode 120 (side B). The narrowportion of the supplementary virtual electrode 130 restricts theelectric field component of the supplementary electrode 120 in thatregion of the wafer holder 140 to reduce the influence of thesupplementary electrode 120 in a corresponding region of the wafer W.Conversely, the wide portion of the supplementary virtual electrode 130increases the electric field component of the supplementary electrode120 in the region where the wafer W is further away from thesupplementary electrode 120. The supplementary virtual electrode 130,therefore, self-compensates for misalignment between the wafer holder140 and the vessel 110 because the shape of the aperture that definesthe supplementary virtual electrode 130 is defined, at least in part, bythe relative position between the wafer holder 140 and the correspondingstructure of the vessel 110. The apparatus 100 accordingly provides arobust system that is less sensitive to misalignment between the waferholder 140 and the vessel 110.

Another feature of the apparatus 100 is that the supplementary electrode120 can be located very close to the supplementary virtual electrode130, and the supplementary virtual electrode 130 is located close to theperimeter of the wafer W. The supplementary electrode 120 is locatedabove the member 112 and proximate to the wafer holder 140 so that thedistance to the supplementary virtual electrode 130 is short compared tothe location of thief electrodes in prior art devices. This arrangementcauses only a small voltage drop between the supplementary electrode 120and the supplementary virtual electrode 130. The resistance between thesupplementary electrode 120 and the supplementary virtual electrode 130is accordingly a function of the distance between these components. As aresult, local resistance changes caused by a misalignment between thewafer holder 140 and the vessel 110 can constitute a significantpercentage of the resistance value between a wafer W that is perfectlyaligned with the supplementary electrode 120. The different widths ofthe different regions of the supplementary virtual electrode 130,therefore, will have a significant influence on the electric field atthe perimeter of the wafer W to counteract non-uniformities caused bythe misalignment. The close proximity of the supplementary virtualelectrode 130 to the perimeter of the wafer W further enhances theability of the system to counteract even small misalignments between thewafer holder 140 and the vessel 110.

The apparatus 100 is particularly useful for plating materials ontowafers that are not rotated during the plating cycle. For example,magnetic media are fabricated by holding the wafer W stationary during aplating cycle to maintain the desired orientation between the magneticfield and the wafer W. In these applications any misalignment betweenthe wafer holder and the vessel will cause a corresponding offset in theelectric field relative to the surface S of the wafer W. The apparatus100 with the supplementary electrode 120 and the supplementary virtualelectrode 130 counteracts the non-uniformities caused by a misalignmentbetween the wafer holder 140 and the vessel 110 to enable thesupplementary electrode 120 to be spaced apart from the wafer holder andoperate as a thief electrode in such applications.

Another advantage of the apparatus 100 is that it reduces the problemsassociated with particle contamination and makes it easier to maintainthe supplementary electrode 120. More specifically, because thesupplementary electrode 120 is spaced apart from the wafer W and residesin the exit flow of the processing fluid F, particles dislodged from thesupplementary electrode 120 are carried away from the wafer W and out ofthe vessel 110. Such particles can then be filtered out of theprocessing fluid F before it is recycled to the vessel 110. Moreover,because the supplementary electrode 120 is positioned above the vessel110, it is easily removed for maintenance by detaching the mount 150from the vessel 110 without having to drain the vessel below the member112 and/or disassemble the vessel 110. This feature will greatly enhancethe ability to clean the supplementary electrode 120 without incurringsignificant downtime. As such, the apparatus 100 is also particularlyapplicable and advantageous in applications in which the supplementaryelectrode 120 is a thief electrode that is subject to frequent cleaning.

The apparatus 100 is also advantageous because it enhances the abilityto control the current density at the perimeter of the wafer withoutchanging the geometry of the chamber. As explained above, many existingplating chambers without thief electrodes use mechanical shields in thevessel to limit the current density at the edge of the wafer. Althoughthese systems are useful, it is cumbersome to change such shields toadapt a chamber to process a different type of wafer. Moreover, suchshields may limit the ability to provide the desired current to theperimeter of the wafer W at certain times of the plating cycle. Theapparatus 100 improves the control of the current density at theperimeter of the wafer W because the supplementary virtual electrode 130is located in, or at least proximate to, the processing zone Z. Forexample, when the supplementary virtual electrode 130 is located aboveany shields in the reactor and/or a virtual anode(s) in the vessel, thesupplementary virtual electrode 130 has a strong influence on thecurrent density at the perimeter of the wafer W. This configurationprevents the geometry of the vessel 110 from limiting the electric fieldcomponent of the supplementary electrode 120. The current density in theperimeter of the wafer W, therefore, can be more fully controlled duringa plating cycle by changing the current through the supplementaryelectrode 120 to compensate for electrical properties at the surface ofthe wafer W and in the processing fluid without being limited by thegeometry of the vessel. As a result, the apparatus 100 can be adaptedfor plating different types of wafers and/or control of the currentdensity during plating cycles by merely controlling the current throughthe supplementary electrode 120 without having to change the physicalgeometry of the chamber. This feature will greatly enhance the efficacyof plating onto thin seed layers or directly onto barrier layers whereit is necessary to overcome the significant drop in current densityacross the wafer during the initial stages of the plating cycle. Thisfeature is similarly important to applications with a high density offeatures for analogous reasons.

FIG. 5 is a side view of an apparatus 500 in accordance with anotherembodiment of the invention in which some features are shown in crosssection and other features are shown schematically. Like referencenumbers refer to like components throughout FIGS. 1-5. The apparatus 500includes a counter electrode 170 in the vessel 110 and a power supply180 operatively coupled to the contacts 144 and the counter electrode170. In this embodiment, the counter electrode 170 is a single electrodein the vessel 110. The vessel can contain a single processing fluid thatflows upwardly to the wafer W, or the apparatus 500 can further includean ion exchange membrane 190 in the vessel 110, a first cell 192 on oneside of the ion-membrane 190 for an anolyte or a catholyte, and a secondcell 194 on the other side of the ion-exchange membrane 190 for theother of the catholyte or the anolyte. Suitable configurations for theion-exchange membrane 190, the first cell 192, and the second cell 194are described and shown in U.S. Patent Publication Nos.US2003-0127337A1; US2005-0121317A1; US2005-0121326A1; andUS2006-0144699A1, which are incorporated herein by reference. Theapparatus 500 is accordingly an electroplating or electropolishingsystem that can operate in the same manner as the apparatus 100described above with reference to FIGS. 1-4.

FIG. 6 is a side view of an apparatus 600 in accordance with stillanother embodiment of the invention in which some features are shown incross-section and other features are shown schematically. Like referencenumbers refer to like components throughout FIGS. 1-6. The apparatus 600is similar to the apparatus 500 described above with reference to FIG.5, but the apparatus 600 includes a plurality of independently operablecounter electrodes 170 a-c that are electrically coupled to a pluralityof independent power sources 182, 184 and 186, respectively. Inoperation, the counter electrodes 170 a-c can establish an electricfield within the apparatus 600 for plating material onto the wafer W orremoving material from the wafer W. Suitable multiple-electrodeapparatus and methods for operating such apparatus are disclosed in U.S.Patent Publication Nos. US2003-0062258A1; US2002-0139678A1;US2003-0038035A1; US2005-0034809A1; US2005-0050767A1; andUS2005-0087439A1 and U.S. Pat. Nos. 6,569,297; 6,660,137; 6,916,412;7,020,537; and 7,160,421, all of which are incorporated herein byreference. The apparatus 600 is accordingly an electroplating orelectropolishing system that can operate in the same manner as theapparatus 100 and 500 described above with reference to FIGS. 1-5.

The apparatus 600 is particularly useful for controlling the currentdensity to compensate for variations in the bath conductivity, seedlayer conductivity, and different thickness profile requirements forvarious wafers. During the initial part of a plating cycle fordepositing copper onto a very thin seed layer or directly onto a barrierlayer, the perimeter portion of the wafer has a much higher currentdensity than the center portion because of the resistance of the seedlayer or barrier layer. However, after enough copper has plated onto thewafer, the current density is much more uniform across the wafer. Theapparatus 600 can compensate for such variations in the current densityduring the plating cycle by dynamically varying the current applied toeach of the counter electrodes 170 a-c and the supplementary electrode120. In one specific embodiment of using the apparatus 600, thesupplementary electrode 120 is a cathodic thief electrode, and thecounter electrodes 170 a-c are anodes that operate at different currentlevels. As material is plated onto the wafer, the current to the thiefmay be reduced and the current to each of the counter electrodes 170 a-cmay be varied to create the desired plating profile on the workpiece.Other aspects of using the apparatus 600 can include varying thecurrents to the counter electrodes 170 a-c and the supplementaryelectrode 120 to compensate for changes in the bath conductivity overtime as well as providing good control to plate different thicknessprofiles and different types of wafers.

FIG. 7 is an isometric view of an apparatus 700 in accordance with aparticular embodiment of the invention, and FIG. 8 is a cross-sectionalview of the apparatus 700. Like reference numbers refer to likecomponents throughout FIGS. 1-8. As such, the apparatus 700 includes thesupplementary electrode 120, supplementary virtual electrode 130, waferholder 140, and mount 150. For a 200 mm wafer W, a representative widthof the supplementary virtual electrode 130 is about 13 mm. The apparatus700 further includes a vessel 710 having a lower portion 712, an upperportion 714 with a horizontal processing zone Z (FIG. 7) at which thewafer W is processed, and an interface 716 between the lower portion 712and the upper portion 714. The interface 716 can be a gasket, filterand/or an ion-exchange membrane.

The apparatus 700 further includes one or more counter electrodes 730,such as the three that are shown and identified as first, second andthird electrodes 730 a, 730 b and 730 c, respectively. Accordingly, thelower portion 712 is also an electrode support having annularcompartments 732 with upwardly extending walls that terminate near theinterface 716. Each electrode 730 a-c is positioned in a correspondingannular compartment 732. The upper portion 714 has channels 740corresponding to the compartments 732, and each channel 740 has at leastone upwardly extending dielectric wall to define virtual counterelectrodes 750 a-c corresponding to the electrodes 730 a-c,respectively. The electrodes 730 a-730 c, each of which can beindependently controlled, can accordingly operate via the correspondingvirtual counter electrodes 750 a-c at locations below the supplementaryvirtual electrode 130.

In operation, the processing fluid enters the vessel 710 through a fluidinlet 718 that passes through a center opening in the lower portion 712and an opening in the center of the innermost anode 730 a. Theprocessing fluid proceeds to a flow control assembly 720 that directsthe processing fluid generally radially inward after which the fluidturns upwardly and flows toward the processing zone Z. A portion of theprocessing fluid flows through an opening defined by the inner edge 114and over the rim 116 and the brim 154 as described above with respect toFIGS. 3 and 4. Another portion of the processing fluid flows downwardlythrough the channels 740, into the electrode compartments 732, andthrough an exit outlet in the lower portion 712.

The apparatus 700 can further include an agitator 760 between thevirtual anodes 750 a-c and the wafer holder 140. The agitator 760includes a plurality of agitator elements 762 that can be elongated barsarranged generally parallel to each other. The agitator 760 reciprocatesin a direction generally transverse to the longitudinal dimension of theagitator elements 762 to agitate the processing fluid in the processingzone Z. Suitable agitators are disclosed in U.S. Patent Publication Nos.US2005-0006241A1; US2005-0000817A1, and US2004-0245094A1; andUS2007-0151844A1, all of which are incorporated herein by reference. Theapparatus 700 is particularly useful for applications that include anagitator and hold the wafer stationary during processing because thedielectric walls that define the virtual counter electrode 750 a-c arelocated a sufficient distance below the wafer W to provide room for theagitator so that the agitator 760 does not greatly disturb theaxis-symmetric electric field. Also, locating the virtual thief openingat the processing zone Z above the agitator 760 minimizes the disruptionthat the agitator may have on the thief electric field contribution.Therefore, the apparatus 700 having a virtual thief opening proximate tothe workpiece holder 140 and above the agitator 760 in combination witha multiple anode system having virtual anodes located sufficiently belowthe wafer holder 140 to provide room for the agitator achieves superiorcontrol of the plating performance.

Another feature of the apparatus 700 is that the third virtual anodeopening 750 c has an outer diameter that is greater than the outerdiameter of the seal against the perimeter of the wafer W. This featureallows the wafer holder 140 to be misaligned relative to the vessel 710without having the perimeter of either side of the wafer W shielded bythe outer diameter of the third virtual electrode 750 c. As a result,the apparatus 700 minimizes the sensitivity to misalignment between thewafer holder 140 and the vessel 710 as well as radio manufacturingtolerances.

In an alternative embodiment, the vessel 710 can be configured tocontain an anolyte separately from a catholyte. For example, the lowerportion 712 can be a first cell and the upper portion 714 can be asecond cell. The lower portion 712 can be one of an anolyte or catholytecell through which a flow of a first processing fluid passes, and theupper portion 714 can be the other of a catholyte or anolyte cellthrough which a flow of a second processing fluid passes. The interface716 in this type of reactor is an ion-exchange membrane that separatesthe first processing fluid in the lower portion 712 and from the secondprocessing fluid in the upper portion 714. The ion-exchange membrane isconfigured to prevent the first and second fluids from passing betweenthe lower portion 712 and the upper portion 714, but to allow thedesired ion transfer across the membrane to carry out theelectrochemical process. Suitable vessels with multiple-electrodesand/or ion-exchange membranes are described and shown in U.S. PatentPublication Nos. US2005-0121317A1; US2005-0121326A1; US2006-0144699A1;and US2005-0087439A1, all incorporated herein by reference.

FIG. 9 is a cross-sectional view illustrating an apparatus in accordancewith another embodiment of the invention. Like reference numbers referto like components in FIGS. 1-9. In this embodiment, the vessel 110includes a member 902 that is similar to the member 112 described abovewith reference to FIGS. 1-4. The member 902 includes the inner edge 114and the rim 116, but there is not an outlet at member 902. The apparatusalso includes a mount 910 that is attached to, or integral with, thevessel 110 to form a compartment 920 in which the supplementaryelectrode 120 is positioned. The mount 910 has a brim that defines asingle weir over which the processing fluid flows outwardly to theperimeter 918 of the vessel 110.

FIG. 10 is a cross-sectional view of a portion of an apparatus inaccordance with another embodiment of the invention. Like referencenumbers refer to like embodiments in FIGS. 1-10. In this embodiment, thevessel 110 includes the member 902, a mount 1010 above the member thatdefines a compartment 1012, and a supplementary electrode 1020 having afirst portion 1022 in the compartment 1012 and a second portion 1024outside of the compartment 1012. The first portion 1024 defines a flowchannel such that the processing fluid flows along the supplementaryelectrode 1020. More specifically, the processing fluid can flowoutwardly along an underside of the first portion 1022 and then inwardlyrelative to a central axis of the vessel 110 along an upper side of thefirst portion 1022. The supplementary electrode 1020 can be attached tothe mount 1010 using tabs in the compartment and/or the second portion1024 can be attached to the brim of the mount 1010. The apparatusillustrated in FIG. 10 eliminates the need to balance the flow betweentwo exits as shown in the apparatus 100 illustrated in FIGS. 1-4. Theapparatus illustrated in FIG. 10 may also provide satisfactory flow overthe brim at a lower total overflow rate, and it may be less susceptibleto ingesting bubbles as an agitator oscillates back and forth because itcreates a longer path from the brim openings to the wafer W.

From the foregoing, it will be appreciated that specific embodiments ofthe invention have been described herein for purposes of illustration,but that various modifications may be made without deviating from thespirit and scope of the invention. For example, the member 112 may havedifferent configurations, or the virtual supplementary electrode 130 mayhave a different location and/or orientation (e.g., inclined relative tothe plane of the wafer or shaped by a different portion of the vessel).Additionally, the supplementary electrode 120 can be a de-platingelectrode either in addition to or in lieu of being a thief electrode.Such de-plating electrodes can be used to de-plate material from thecontacts of the wafer holder. In still additional embodiments, thesupplementary electrode 120 can operate as another counter electrode.One example of this may be forward-reverse pulse plating. During theforward-current portion of the waveform, the supplementary electrode canfunction as a thief or cathode, while the counter electrodes in thevessel function as anodes. During the reverse-portion of the currentwaveform, the supplementary electrode can function as an anode whereasthe counter electrodes in the vessel function as cathodes. In stillother embodiments, the supplementary electrode can function as an anodewhile the counter electrodes in the vessel also function as additionalanodes. In still additional embodiments, the shape of the inner edgeand/or the shape of the outer surface of the wafer holder can beconfigured to shape the virtual supplementary electrode. The inner edgeof the vessel and/or the outer edge of the wafer holder can be changeddynamically during or between processing cycles, or the shape of thesefeatures can be changed by replacing circular components with differentshapes (e.g., ovals, ellipses, eccentric shapes, etc.). Certain featuresof the invention described in the context of the foregoing particularembodiments may be combined or eliminated in other embodiments.Accordingly, the invention is not limited except as by the appendedclaims.

1. A method for electrochemically processing a substrate, comprising:holding the substrate in a holder in a vessel; establishing an electricfield in a processing fluid in the vessel by passing electric currentthrough a conductive layer on the substrate, at least one counterelectrode in the vessel, and a supplementary electrode; with the vesselhaving a cylindrical sidewall and an annular member projecting radiallyinwardly from the cylindrical sidewall; the annular member having aninner edge, with an annular gap formed between the inner edge and theholder, and with the electric current passing through the supplementaryelectrode also passing through processing fluid in the annular gap; andcompensating for misalignment between the substrate and the counterelectrode via the electric current passing through the processing fluidin the annular gap.
 2. The method of claim 1 with the supplementaryelectrode inclined at a non-zero angle relative to the supplementaryvirtual electrode.
 3. The method of claim 1 further includingcounteracting an offset of the electric field relative to the waferassociated with an offset between the wafer holder and the vessel byshaping the supplementary virtual electrode to have a first width at afirst side of the wafer holder and a second width different than thefirst width at a second side of the wafer holder.
 4. The method of claim1 wherein the compensating comprises shaping the annular gap to have afirst width at a first side of the holder and a second width differentthan the first width at a second side of the holder.
 5. The method of 1wherein the supplementary electrode is located above the supplementaryvirtual electrode.
 6. The method of claim 1 wherein the supplementaryelectrode is located above the processing zone, and further comprisingplating onto the supplementary electrode to thieve material relative toa perimeter of the wafer.
 7. The method of claim 1 wherein thesupplementary electrode is located above the counter electrode, andfurther comprising de-plating material using the supplementaryelectrode.
 8. The method of claim 1 wherein the supplementary electrodeis located above the processing zone, and further comprising de-platingmaterial using the supplementary electrode.
 9. The method of claim 1wherein the vessel includes a member having an inner edge, a rim abovethe inner edge, and a perimeter, and wherein the supplementary electrodeis located above the member at a radial position between the inner edgeand the perimeter, and further comprising plating onto the supplementaryelectrode to thieve material relative to a perimeter of the wafer. 10.The method of claim 10 further comprising shaping an electric fieldcomponent using a supplementary virtual electrode having an apertureformed, at least in part, by the inner edge of the member, and furthercomprising plating onto the supplementary electrode to thieve materialrelative to a perimeter of the wafer.
 11. The method of claim 1 with thesupplementary virtual electrode comprising an aperture filled withprocessing fluid, further comprising compensating for misalignmentbetween the wafer and the counter electrode by passing electric currentthrough processing fluid in the aperture, and with the aperture formed,at least in part, by a portion of the vessel at the processing zone anda portion of the wafer holder.
 12. The method of claim 1 furthercomprising establishing the electric field using a plurality of counterelectrodes and operating the counter electrodes independently from eachother and the supplementary electrode.
 13. The method of claim 1 withthe annular gap oriented in a substantially horizontal plane andproviding a virtual supplementary electrode substantially parallel tothe substrate.